When Ben Wells, president of Wells R&D (Lincoln, MA), a maker of custom testing solutions for the semiconductor and optical industries, was building a test instrument, he needed to way to stack and ...

Modern semiconductor fabrication involves aligning silicon wafers and photolithography masks to nanometre precision. As the industry shifts from using 200 mm diameter wafers to 300 mm wafers, ...

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, ...

Cognex at Semicon Japan announced the In-Sight 1820 vision-based wafer pre-aligner. Utilizing proprietary Cognex NotchMax alignment technology, the 1820 vision system provides precise noncontact ...

A technique which will allow silicon wafers to be stacked accurately and inexpensively in 3-D structures has been developed by researchers at the University of Southampton. According to Dr Michael ...

Parallel piezo aligners with fly height sensors enable faster PIC wafer testing. (Nanowerk News) PI (Physik Instrumente) announced a new technology platform for electro-optical wafer-level testing ...

In what is being described as a breakthrough for the future of die-to-wafer (D2W) bonding, CEA-Leti and Intel have optimised a hybrid direct-bonding, self-assembly process that has the potential to ...

SAN DIEGO – June 2, 2022 – In a breakthrough for the future of die-to-wafer (D2W) bonding, CEA-Leti and Intel have optimized a hybrid direct-bonding, self-assembly process that has the potential to ...

An optical method for mask alignment in double-sided lithography has been developed by a team at the University of Hagen in Germany (Appl. Opt. 40 5052). The technique, which is based on the ...

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and ...