Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.

This insatiable demand for data is what led to the need for JEDEC to introduce the JESD204 standard for a high-speed serial link between data converters and logic devices. The “B” revision of the ...

For high-speed signal sampling and processing applications that need an array of synchronized analog-to-digital converters (ADCs), the ability to de-skew and match latency variation across the ...

One of the challenges facing those developing networks featuring wirelessly connected devices is maintaining a common clock time. A popular way of doing this is by using Network Time Protocol (NTP), a ...