Editor's note: Consultant and ASIC designer Tom Moxon has evaluated deep submicron IC design flows using open-source cores and new EDA tools. He will report his findings in a five-part article series ...

TSMC has certified the Cadence digital and custom/analog design flows for its N4P and N3E process technologies. These design flows support TSMC’s latest Design Rule Manual (DRM) and FINFLEX technology ...

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

In the realm of high-performance IC (integrated circuit) design, symmetry is not just an aesthetic preference—it’s a critical factor for ensuring proper device functionality, especially in analog and ...

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows have achieved certification for TSMC’s latest N2 Design Rule Manual ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, ...

Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tape-outs. The reference flows, ...

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles ...